System-On-Chip Test Architectures

Nanometer Design for Testability Volume .

von Charles E Stroud, Nur A Touba, Laung-Terng Wang

896 Seiten, Hardcover

Kurzbeschreibung des Verlags

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

• Themen: Kunst Design, industrielle und kommerzielle Kunst, Illustration Produktdesign
• ISBN: 9780123739735
• Sprache: Englisch
• Erscheinungsdatum: 01.11.2007
• Größe: 241 x 197 mm
• Verlag: Elsevier Science