Designing Reliable and Efficient Networks on Chips

von Srinivasan Murali

198 Seiten, Hardcover

Kurzbeschreibung des Verlags

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.

• Reihe: Lecture Notes in Electrical Engineering
• Themen: Technologie, Ingenieurswissenschaft, Landwirtschaft, Industrieprozesse Elektronik, Nachrichtentechnik Elektronik Schaltkreise und Komponenten (Bauteile)
• ISBN: 9781402097560
• Sprache: Englisch
• Erscheinungsdatum: 21.04.2009
• Größe: 23.5 x 15.5 cm
• Verlag: Springer Netherland